1. Field of the Invention
The present invention relates to a plasma display apparatus and a method of driving the same, and more particularly to a plasma display apparatus capable of improving contrast and a method of driving the same.
2. Description of the Background Art
A plasma display panel (PDP) emits light from a fluorescent body by ultraviolet (UV) rays generated when an inactive mixed gas such as He+Xe, Ne+Xe, and He+Xe+Ne is discharged to display images. Such a PDP is easily made thin and large and provides significantly improved picture quality due to recent development of technology.
Referring to FIG. 1, a conventional three-electrode AC surface discharge type PDP includes scan electrodes Y1 to Yn and sustain electrodes Z and address electrodes X1 to Xm that intersect the scan electrodes Y1 to Yn and the sustain electrodes Z.
Cells 1 for displaying one of red, green, and blue are formed in the intersections of the scan electrodes Y1 to Yn, the sustain electrodes Z, and the address electrodes X1 to Xm. The scan electrodes Y1 to Yn and the sustain electrodes Z are formed on a top substrate that is not shown. A dielectric layer and an MgO protective layer that are not shown are laminated on the top substrate. The address electrodes X1 to Xm are formed on a bottom substrate that is not shown. A partition wall for preventing optical and electrical interference between adjacent cells is horizontally formed on the bottom substrate. A fluorescent body excited by vacuum UV to emit visible rays is formed on the surfaces of the bottom substrate and the partition wall. A mixed gas required for discharge such as He+Xe, Ne+Xe, and He+Xe+Ne is implanted into a discharge space between the top substrate and the bottom substrate.
In order to realize gray scales of an image, a PDP divides a frame into various sub fields having different numbers of time of light emission to perform time division driving. Each sub field is divided into a reset period for initializing the entire screen, an address period for selecting a scan line and for selecting a cell from the selected scan line, and a sustain period for realizing gray scales in accordance with the number of times of discharge. For example, when an image is displayed by 256 gray scales, as illustrated in FIG. 2, a frame period (16.67 ms) corresponding to 1/60 second is divided into eight sub fields SF1 to SF8. As described above, each of the eight sub fields SF1 to SF8 is divided into the reset period, the address period, and the sustain period. Meanwhile the reset period and the address period of the respective sub fields are the same, the sustain period in each sub field and the number of sustain pulses assigned to the sustain period increase in the ratio of 2n (n=0, 1, 2, 3, 4, 5, 6, and 7).
FIG. 3 illustrates an example of driving waveforms applied to a PDP.
Referring to FIG. 3, according to a method of driving the conventional PDP, in each sub-field (SFi, SFi+1), set-up discharge is generated using a rising ramp waveform Ramp-up and set-down discharge is generated using a falling ramp waveform Ramp-dn to initialize cells.
The rising ramp waveform Ramp-up is simultaneously supplied to all of the scan electrodes Y in the reset period of each sub-field (SFi, SFi+1). At the same time, 0[V] is supplied to the sustain electrodes Z and the address electrodes X. Set-up discharge is generated by the rising ramp waveform Ramp-up in the cells of the entire screen between the scan electrodes Y and the address electrodes X and the scan electrodes Y and the sustain electrodes Z. Positive (+) wall charges are accumulated on the address electrodes X and the sustain electrodes Z and negative (−) wall charges are accumulated on the scan electrodes Y due to the set-up discharge.
Subsequent to the rising ramp waveform Ramp-up, the falling ramp waveform Ramp-dn that starts to fall from a sustain voltage Vs lower than the set-up voltage Vsetup of the rising ramp waveform Ramp-up and that falls to a negative specific voltage is simultaneously supplied to the scan electrodes Y. At the same time, a bias voltage Vz is supplied to the sustain electrodes Z and 0[V] is supplied to the address electrodes X. The bias voltage Vz may be determined as the sustain voltage Vs. When the falling ramp waveform Ramp-dn is supplied, set-down discharge is generated between the scan electrodes Y and the sustain electrodes Z. Excessive wall charges that are not required for address discharge among the wall charges generated during the set-up discharge are erased by the set-down discharge.
In the address period of each sub-field (SFi, SFi+1), scan pulses Scp of a negative writing voltage −Vw are sequentially supplied to the scan electrodes Y and data pulses Dp of a positive data voltage Vd synchronized with the scan pulse Scp are supplied to the address electrodes X. At this time, the voltages of the scan pulses Scp and the data pulses Dp and the wall voltage generated in the reset period are added to each other to generate address discharge in the cell to which the data pulses Dp are supplied.
In the sustain period of each sub-field (SFi, SFi+1), sustain pulses Susp of the sustain voltage Vs are alternately supplied to the scan electrodes Y and the sustain electrodes Z. In the cell selected by the address discharge, sustain discharge, that is, display discharge is generated between the scan electrodes Y and the sustain electrodes Z whenever the wall voltage in the cell and the sustain voltage Vs are added to each other to supply each sustain pulse Susp. The sustain period and the number of sustain pulses Susp vary in accordance with the brightness weight given to a sub-field.
An erasing signal for erasing remaining charges in a cell may be supplied to the scan electrodes Y or the sustain electrodes Z after the sustain discharge is completed.
According to the driving waveform illustrated in FIG. 3, at the point of time where the set-down discharge is completed, the set-down voltage of the falling ramp waveform Ramp-dn is fixed to potential higher than the negative writing voltage −Vw of the scan pulses Scp by ΔV. Since the falling ramp waveform Ramp-dn reduces the positive wall charges excessively accumulated on the address electrodes X by the set-up discharge, when the set-down voltage of the falling ramp waveform Ramp-dn is fixed to the potential higher than the negative writing voltage −Vw, more positive wall charges may reside on the address electrodes X. According to the driving waveform illustrated in FIG. 3, since it is possible to reduce the voltage (Vd, −Vw) required for the address discharge, it is possible to reduce a PDP by a low voltage.
According to the conventional PDP driven by the above-described method, it is possible to stably display images corresponding to the gray scales of sub-fields. However, according to the conventional PDP, contrast deteriorates due to light generated in the reset period.
In more detail, as illustrated in FIG. 3, according to the method of driving the conventional PDP, the rising ramp waveform Ramp-up is supplied in each reset period of all the sub-fields included in one frame. Therefore, the set-up discharge is generated in each reset period of all of the sub-fields. The set-up discharge is generated by the rising ramp waveform Ramp-up that rises to the set-up voltage Vsetup that is higher than the sustain voltage Vs such that desired wall charges may be formed in all of the discharge cells. Therefore, predetermined light is generated by the set-up discharge generated by the rising ramp waveform Ramp-up in all of the discharge cells, which deteriorates the contrast of a PDP.